Chris M.

Here are some of the steps to get FreeRTOS and newlib (gcc) to work correctly on the STM32F10x, a Cortex-M3 ARM processor. Configure the priority bits Per  the FreeRTOS page about the Cortex M3 and M4 , the priority bits should be assigned to be preempt priority by calling NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );  If you or any start up related code you are using isn't doing this you may end up with odd behavior or bus faults. Map FreeRTOS tasking functions to CMSIS vector handlers Per this post  you'll want to map the FreeRTOS handlers for vPortSVCHandler, xPortPendSVHandler and xPortSysTickHandler to the CMSIS handlers. A readelf of the elf file of my example application was showing the default interrupt handler was being used for those interrupts, which meant FreeRTOS wasn't handling the interrupts it needed to function correctly. The CMSIS default handlers are weakly bound so having other definitions with the same names will override these, causing th...

This information may apply to other cortex series processors but is written from practical experience with the Cortex-M3. Imprecise bus access faults are ambiguous, as noted by the term "imprecise". Compared to precise bus errors, imprecise errors are much trickier to debug and especially so without a deep understanding of arm processors and assembly language. Imprecise and precise flags are found in the BusFault status register, a byte in the CFSR (Configurable Fault Status Register). BusFault status register bits The definition for imprecise and precise bits is: [2] IMPRECISERR Imprecise data bus error: 0 = no imprecise data bus error 1 = a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the BFAR. This is an asynchronous fault. Therefore, if it is detected when the priority of the current pr...

CMSIS-SVD is "Cortex Microcontroller Software Interface Standard" "System View Description". This is an ARM standard format for describing the registers and their bitfields for the Cortex-M series of ARM processors. If you have an account on the Arm website you can visit the STMicro cmsis page  where you can download the svd files for various STMicro processors. The STM32F10x svd files however appear to be missing important things like the system control block . This is an issue because I've been using the Eclipse plugin EmbSysRegView  to browse cpu registers during debug. The system control block is important because it contains various status registers that report fault status. These registers can help to locate issues in code or configuration. I posted a support question with ST and on their forums to see why their CMSIS-SVD doesn't appear to include all of the processors registers but I'll probably end up modifying the other EmbSysRegView proc...

A test application using FreeRTOS and an arm cross compiler was landing in the default exception handler during the start up code in main(). Because several of the exception handlers are still using the default exception handler the debugger indicates WWDG_IRQHandler. Some googling turned up this post  but while mapping the FreeRTOS handlers with #defines did correct something I had missed it wasn't the cause of the exceptions. Single stepping through the code narrowed the issue down to a call to malloc(), in at a label called _malloc_from_thumb(). The particular instruction was "bx pc". When the 'bx pc' was executed the processor jumped directly to the watchdog isr handler. Next I ran 'objdump -d -S -l' on the elf file and started looking at the code and assembly. main() looks like: _malloc_from_thumb(): looks like: You can see that this function has a couple of 16 bit thumb instructions and then a 32 bit arm instruction. Its purpose, a...